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| PRELIMINARY Logic Block Diagrams CY7C1481V33 - 2M x 36 MODE (A[1;0]) 2 CLK ADV ADSC ADSP A[20:0] GW BWE BW d BWc D BWb D BWa CE1 CE2 CE3 D BURST Q0 CE COUNTER Q1 CLR Q 21 19 D ADDRESS CE REGISTER D DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS ENABLE CE REGISTER Q 19 21 CY7C1481V33 CY7C1483V33 CY7C1487V33 2M X36 MEMORY ARRAY D Q Q Q 36 Q 36 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL INPUT REGISTERS CLK DQa,b,c,d DPa,b,c,d CY7C1483V33 - 4M X 18 MODE (A[1;0]) 2 CLK ADV ADSC ADSP A[21:0] GW BWE BW b BWa BURST Q0 CE COUNTER Q1 CLR Q 22 20 D ADDRESS CE REGISTER D DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS Q 20 22 4M X 18 MEMORY ARRAY D Q CE1 CE2 CE3 18 D ENABLE CE CE REGISTER Q 18 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL INPUT REGISTERS CLK DQa,b DPa,b Document #: 38-05284 Rev. *A Page 2 of 30 PRELIMINARY Logic Block Diagrams (continued) CY7C1487V33 - 1M x72 MODE (A[1;0]) 2 CLK ADV ADSC ADSP A[19:0] GW BWE BW h BWg D BWf D BWe D BW d D BWc D BWb D BWa CE1 CE2 CE3 BURST Q0 CE COUNTER Q1 CLR Q 20 18 D ADDRESS CE REGISTER D DQh, DPh BYTEWRITE REGISTERS DQg, DPg BYTEWRITE REGISTERS DQf, DPf BYTEWRITE REGISTERS DQe, DPe BYTEWRITE REGISTERS DQd, DPd BYTEWRITE REGISTERS DQc, DPc BYTEWRITE REGISTERS DQb, DPb BYTEWRITE REGISTERS DQa, DPa BYTEWRITE REGISTERS ENABLE CE REGISTER Q 18 20 CY7C1481V33 CY7C1483V33 CY7C1487V33 1M X72 MEMORY ARRAY D Q Q Q Q Q Q Q 72 D Q 72 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL INPUT REGISTERS CLK DQa,b,c,d,e,f,g,h DPa,b,c,d,e,f,g,h . Selection Guide CY7C1481V33-150 CY7C1481V33-133 CY7C1481V33-117 CY7C1481V33-100 CY7C1483V33-150 CY7C1483V33-133 CY7C1483V33-117 CY7C1483V33-100 CY7C1487V33-150 CY7C1487V33-133 CY7C1487V33-117 CY7C1487V33-100 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 5.5 TBD TBD 6.5 TBD TBD 7.5 TBD TBD 8.5 TBD TBD Unit ns mA mA Document #: 38-05284 Rev. *A Page 3 of 30 PRELIMINARY Pin Configurations 100-pin TQFP (Top View) CY7C1481V33 CY7C1483V33 CY7C1487V33 A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1481V33 (2M X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb NC NC DQb NC DQb VDDQ VDDQ VSSQ VSSQ NC DQb NC DQb DQb DQb DQb DQb VSSQ VSSQ VDDQ VDDQ DQb DQb DQb DQb NC VSS VDD NC NC VDD VSS ZZ DQa DQb DQa DQb VDDQ VDDQ VSSQ VSSQ DQa DQb DQa DQb DQa DPb NC DQa VSSQ VSSQ VDDQ VDDQ NC DQa NC DQa DQPa NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1483V33 (4M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 A A VSS VDD A A A A A A A A A MODE A A A A A1 A0 A VSS VDD Document #: 38-05284 Rev. *A A A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 4 of 30 PRELIMINARY Pin Configurations (continued) CY7C1481V33 (2M x 36) 3 4 5 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO CY7C1481V33 CY7C1483V33 CY7C1487V33 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A A A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A A TMS 6 A A A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A A NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ CY7C1483V33 (4M x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC A VDDQ 2 A A A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A A A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC 7 VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ Document #: 38-05284 Rev. *A Page 5 of 30 PRELIMINARY Pin Configurations (continued) 165-Ball Bump FBGA (This package is offered on opportunity basis) CY7C1481V33 (2M x 36) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R NC NC DPc DQc DQc DQc DQc NC DQd DQd DQd DQd DPd NC MODE CY7C1481V33 CY7C1483V33 CY7C1487V33 2 A A NC DQc DQc DQc DQc VSS DQd DQd DQd DQd NC A A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC 144M DPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DPa A A CY7C1483V33 (4M x 18) - 11 x 15 FBGA 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC DQb DQb DQb DQb DPb NC MODE 2 A A NC DQb DQb DQb DQb VSS NC NC NC NC NC A A 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0 7 BWE GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS TDO TCK 8 ADSC OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 ADV ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A 144M DPa DQa DQa DQa DQa ZZ NC NC NC NC NC A A Document #: 38-05284 Rev. *A Page 6 of 30 PRELIMINARY Pin Configurations (continued) 209-ball BGA (This package is offered on opportunity basis) CY7C1487V33 (1M x72) 1 A B C D E F G H J K L M N P R T U V W DQg DQg DQg DQg DPg DQc DQc DQc DQc NC DQh DQh DQh DQh DPd DQd DQd DQd DQd CY7C1481V33 CY7C1483V33 CY7C1487V33 2 DQg DQg DQg DQg DPc DQc DQc DQc DQc NC DQh DQh DQh DQh DPh DQd DQd DQd DQd 3 A BWSc BWSh VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS VDDQ VSS A A TMS 4 CE2 BWSg BWSd NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI 5 6 7 ADV A NC GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A 8 CE3 BWSb BWSe NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO 9 A BWSf BWSa VSS VDDQ VSS VDDQ VSSQ VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A A TCK 10 DQb DQb DQb DQb DPf DQf DQf DQf DQf NC DQa DQa DQa DQa DPa DQe DQe DQe DQe 11 DQb DQb DQb DQb DPb DQf DQf DQf DQf NC DQa DQa DQa DQa DPe DQe DQe DQe DQe ADSP ADSC NC NC NC VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A BW CE1 OE VDD NC NC NC NC VSS NC NC NC ZZ VDD MODE A A1 A0 Pin Definitions Pin Name A0 A1 A BWa BWb BWc BWd BWe BWf BWg BWh GW I/O InputSynchronous InputSynchronous Pin Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. InputSynchronous InputSynchronous Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d,e,f,g,h and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. BWE Document #: 38-05284 Rev. *A Page 7 of 30 PRELIMINARY Pin Definitions (continued) Pin Name CLK CE1 CE2 CE3 OE I/O InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Pin Description CY7C1481V33 CY7C1483V33 CY7C1487V33 Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.(TQFP Only) Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.(TQFP Only) Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition. DQ a,b,c,d,e,f,g and h are 8 bits wide. DP a,b,c,d,e,f,g and h are 1 bit wide. ADV ADSP InputSynchronous InputSynchronous ADSC InputSynchronous InputStatic InputAsynchronous I/OSynchronous MODE ZZ DQa, DPa DQb, DPb DQc, DPc DQd, DPd DQe, DPe DQf, DPf DQg, DPg DQh, DPh TDO TDI TMS TCK VDD VSS VDDQ VSSQ 144M NC JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only) Synchronous JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.(BGA Only) Synchronous Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous (BGA Only) JTAG serial clock Serial clock to the JTAG circuit. (BGA Only) Power Supply Ground I/O Ground - - Power supply inputs to the core of the device. Should be connected to 3.3V -5% +5% power supply. Ground for the core of the device. Should be connected to ground of the system. Ground for the I/O circuitry. Should be connected to ground of the system. NC. This pin is reserved for expansion to 144Mb. No connects. I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.375V(min.) to VDD(max.) Document #: 38-05284 Rev. *A Page 8 of 30 PRELIMINARY Functional Description Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip enable (CE1, CE2, CE3 on TQFP, CE1 on BGA) asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) Chip Enable asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d,e,f,g,h for CY7C1487V33, BWa,b,c,d for CY7C1481V33 and BWa,b for CY7C1483V33) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. All I/Os are three-stated during a byte write. Because the CY7C1481V33/CY7C1483V33/CY7C1487V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety CY7C1481V33 CY7C1483V33 CY7C1487V33 precaution, DQx are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) Chip Enable (CE1, CE2, CE3 on TQFP, CE1 on BGA) asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC is ignored if ADSP is active LOW. The address presented to A[17:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQx is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. All I/Os are three-stated during a byte write because the CY7C1481V33/ CY7C1483V33/CY7C1487V33 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety precaution, DQx are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1481V33/CY7C1483V33/CY7C1487V33 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Cycle Descriptions Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read None None None None None External External Next Next Next Next Current [1, 2, 3, 4] Add. Used ZZ 0 0 0 0 0 0 0 0 0 0 0 0 CE3 X 1 X 1 X 0 0 X X X X X CE2 X X 0 X 0 1 1 X X X X X CE1 1 0 0 0 0 0 0 X X 1 1 X ADSP X 0 0 1 1 0 1 1 1 X X 1 ADSC 0 X X 0 0 X 0 1 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 OE X X X X X X X 1 0 1 0 1 DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ Hi-Z DQ Hi-Z Write X X X X X X Read Read Read Read Read Read Notes: 1. X = "Don't Care." 1 = HIGH, 0 = LOW. 2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has a single chip select CE1. Document #: 38-05284 Rev. *A Page 9 of 30 PRELIMINARY Cycle Descriptions (continued)[1, 2, 3, 4] Next Cycle Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ZZ "sleep" Add. Used Current Current Current Current Current External Next Next Current Current None ZZ 0 0 0 0 0 0 0 0 0 0 1 CE3 X X X X X 0 X X X X X CE2 X X X X X 1 X X X X X CE1 X 1 1 X 1 0 X 1 X 1 X ADSP 1 X X 1 X 1 1 X 1 X X Sleep Mode Fourth Address A[1:0] 11 10 01 00 ADSC 1 1 1 1 1 0 1 1 1 1 X ADV 1 1 1 1 1 X 0 0 1 1 X CY7C1481V33 CY7C1483V33 CY7C1487V33 OE 0 1 0 X X X X X X X X DQ DQ Hi-Z DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Write Read Read Read Write Write Write Write Write Write Write X Interleaved Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC Description Snooze mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V 2tCYC Min. Max. TBD 2tCYC Unit mA ns ns Document #: 38-05284 Rev. *A Page 10 of 30 PRELIMINARY Write Cycle Descriptions[1, 2] Function (CY7C1481V33) Read Read Write Byte 0 - DQa Write Byte 1 - DQb Write Bytes 1, 0 Write Byte 2 - DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - DQd Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes Function (CY7C1483V33) Read Read Write Byte 0 - DQ[7:0] and DP0 Write Byte 1 - DQ[15:8] and DP1 Write All Bytes Write All Bytes Function (CY7C1487V33)[5] Read Read Write Byte X Write All Bytes Write All Bytes GW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 GW 1 1 1 1 1 0 BWE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X BWd X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X BWE 1 0 0 0 0 X GW 1 1 1 1 0 BWc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BWb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X BWb X 1 1 0 0 X BWE 1 0 0 0 X CY7C1481V33 CY7C1483V33 CY7C1487V33 BWa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X BWa X 1 0 1 0 X BWx X All BW = 1 0 All BW = 0 X Note: 5. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a low logic signal should be applied at clock rise. Any number of byte writes can be enabled at the same time for any given write. Document #: 38-05284 Rev. *A Page 11 of 30 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1483V33/CY7C1481V33/CY7C1487V33 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP) - Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers CY7C1481V33 CY7C1483V33 CY7C1487V33 Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Document #: 38-05284 Rev. *A Page 12 of 30 PRELIMINARY The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. CY7C1481V33 CY7C1483V33 CY7C1487V33 When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05284 Rev. *A Page 13 of 30 PRELIMINARY TAP Controller State Diagram 1[6] TEST-LOGIC RESET CY7C1481V33 CY7C1483V33 CY7C1487V33 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 0 SHIFT-IR 1 0 1 EXIT1-IR 0 1 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0 0 Note: 6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05284 Rev. *A Page 14 of 30 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI CY7C1481V33 CY7C1483V33 CY7C1487V33 2 Instruction Register 1 0 Selection Circuitry TDO 31 30 29 . . 2 1 0 Identification Register . . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range[7, 8] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND VI VDDQ [9, 10] Test Conditions IOH = -4.0 mA IOH = -100 A IOL = 8.0 mA IOL = 100 A Min. 2.4 3.0 Max. Unit V V 0.4 0.2 1.8 -0.5 -5 VDD + 0.3 0.8 5 V V V V A TAP AC Switching Characteristics Over the Operating Range Parameter tTCYC tTF tTH tTL TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW Description Min. 100 Max 10 Unit ns MHz ns ns 40 40 Notes: 7. All Voltage referenced to Ground. 8. Overshoot: VIH(AC) Page 15 of 30 PRELIMINARY TAP AC Switching Characteristics Over the Operating Range (continued)[9, 10] Parameter Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH tTDOV tTDOX TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 10 10 TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 10 10 10 Description Min. CY7C1481V33 CY7C1483V33 CY7C1487V33 Max Unit ns ns ns ns ns ns 20 ns ns Output Times TAP Timing and Test Conditions 1.25V 50 TDO Z0 = 50 CL = 20 pF 0V ALL INPUT PULSES Vih (a) GND tTH tTL Test Clock TCK tTMSS tTMSH tTC YC Test Mode Select TMS t TDIS t TDIH Test Data-In TDI Test Data-Out TDO tTD OV tTDOX Document #: 38-05284 Rev. *A Page 16 of 30 PRELIMINARY Identification Register Definitions Instruction Field Revision Number (31:29) Department Number (27:25) Voltage (28&24) Architecture (23:21) Memory Type (20:18) Device Width (17:15) Device Density (14:12) Cypress JEDEC ID (11:1) ID Register Presence (0) x 18 000 101 00 000 001 010 100 x36 000 101 00 000 001 100 100 x72 000 101 00 000 001 110 100 Architecture type Defines type of memory Defines width of the SRAM. x36 or x18 Defines the density of the SRAM Department number Description Reserved for version number CY7C1481V33 CY7C1483V33 CY7C1487V33 0000011 0000011 0000011 Allows unique identification of SRAM vendor 0100 0100 0100 1 1 1 Indicate the presence of an ID register Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size (x18) 3 1 32 TBD Bit Size (x36) 3 1 32 TBD Bit Size (x72) 3 1 32 TBD Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED Code 000 001 010 011 Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE/PRELOAD 100 RESERVED RESERVED BYPASS 101 110 111 Boundary Scan Order (2M x 36) Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Boundary Scan Order (2M x 36) (continued) Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Page 17 of 30 Document #: 38-05284 Rev. *A PRELIMINARY Boundary Scan Order (2M x 36) (continued) Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD CY7C1481V33 CY7C1483V33 CY7C1487V33 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Boundary Scan Order (4M x 18) (continued) Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Boundary Scan Order (4M x 18) Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Document #: 38-05284 Rev. *A Page 18 of 30 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[12] ............................... -0.5V to VDDQ + 0.5V DC Input Voltage[12] ............................ -0.5V to VDDQ + 0.5V CY7C1481V33 CY7C1483V33 CY7C1487V33 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Range Com'l Ambient Temperature[11] 0C to +70C VDD 3.3V + 5%/ -5% VDDQ 2.375V (min.) VDD(max.) Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[12] GND < VI < VDDQ Input = VSS GND < VI < VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 150 MHz 133 MHz 117 MHz 100 MHz ISB1 Automatic CE Power-down Current--TTL Inputs Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 150 MHz 133 MHz 117 MHz 100 MHz ISB2 Automatic CE Power-down Current--CMOS Inputs Automatic CE Power-down Current--CMOS Inputs Max. VDD, Device Deselected, VIN < 0.3V or VIN > VDDQ - 0.3V, f=0 Max. VDD, Device Deselected, or VIN < 0.3V or VIN > VDDQ - 0.3V f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN > VIH or VIN < VIL, f = 0 All speed grades VDD = Min., IOH = -4.0 mA VDD = Min., IOH = -1.0 mA VDD = Min., IOL = 8.0 mA VDD = Min., IOL = 1.0 mA 3.3V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V 2.5V Input Load Current Input Current of MODE Input Current of ZZ IOZ IDD Output Leakage Current VDD Operating Supply 2.0 1.7 -0.3 -0.3 0.8 0.7 5 30 30 5 TBD TBD TBD TBD TBD TBD TBD TBD TBD Test Conditions Min. 3.135 2.375 2.4 2.0 0.4 0.4 Max. 3.465 VDD Unit V V V V V V V V V V A A A A mA mA mA mA mA mA mA mA mA ISB3 150 MHz 133 MHz 117 MHz 100 MHz All speed grades TBD TBD TBD TBD TBD mA mA mA mA mA ISB4 Automatic CE Power-down Current--TTL Inputs Shaded area contains advance information. Notes: 11. TA is the ambient temperature. 12. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. Document #: 38-05284 Rev. *A Page 19 of 30 PRELIMINARY Capacitance[14] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = VDDQ = 3.3V CY7C1481V33 CY7C1483V33 CY7C1487V33 Max. TBD TBD TBD Unit pF pF pF AC Test Loads and Waveforms OUTPUT Z0 = 50 RL = 50 VDDQ OUTPUT 5 pF R = 351 VL = 1.5 for 3.3V VDDQ = 1.25 for 2.5V VDDQ INCLUDING JIG AND SCOPE (a) R = 317 ALL INPUT PULSES Vdd 10% GND Rise Time: 2 V/ns 90% [13] 90% 10% Fall Time: 2 V/ns (b) (c) Thermal Resistance[14] Parameter QJA QJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board BGA Typ. TBD TBD TQFP Typ. TBD TBD Unit C/W C/W Switching Characteristics Over the Operating Range -150 Parameter Clock tCYC FMAX tCH tCL tCDV tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ Set-up Times tAS Address Set-up Before CLK Rise 1.5 1.5 1.5 1.5 ns Shaded areas contain advance information. Notes: 13. Input waveform should have a slew rate of > 2 V/ns. 14. Tested initially and after any design or process change that may affect these parameters. 15. Unless otherwise noted, test conditions assume signal transition time of 1.5ns, timing reference levels of 1.75V, input pulse levels of 0 to 3.3V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads. 16. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 17. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 18. This parameter is sampled and not 100% tested. -133 Min. 7.5 150 133 2.5 2.5 5.5 2.5 6.5 3.0 2.5 3.5 3.8 3.0 2.5 3.0 0 0 3.0 2.5 2.8 2.8 Max. -117 Min. 8.5 117 3.0 3.0 7.5 3.4 2.5 4.0 3.0 3.5 0 Max. -100 Min. 10 100 Max. Unit ns MHz ns ns 8.5 3.8 4.5 4 ns ns ns ns ns ns ns Description Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW Data Output Valid After CLK Rise OE LOW to Output Valid[14, 16, 18] Data Output Hold After CLK Rise Clock to High-Z[14, 15, 16, 17, 18] Clock to Low-Z[14, 15, 16, 17, 18] Low-Z[15, 16, 18] Min. 6.7 2.5 2.5 Max. Output Times 2.5 2.5 0 OE HIGH to Output High-Z[15, 16, 18] OE LOW to Output Document #: 38-05284 Rev. *A Page 20 of 30 PRELIMINARY Switching Characteristics Over the Operating Range (continued) -150 Parameter tDS tADS tWES tADVS tCES Hold Times tAH tDH tADH tWEH tADVH tCEH Address Hold After CLK Rise Data Input Hold After CLK Rise ADSP, ADSC Hold After CLK Rise BWE, GW, BWx Hold After CLK Rise ADV Hold after CLK Rise Chip Select Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Description Data Input Set-up Before CLK Rise ADSP, ADSC Set-up Before CLK Rise BWE, GW, BWx Set-up Before CLK Rise ADV Set-up Before CLK Rise Chip Select Set-up Min. 1.5 1.5 1.5 1.5 1.5 Max. 1.5 1.5 1.5 1.5 1.5 -133 Min. Max. 1.5 1.5 1.5 1.5 1.5 -117 Min. Max. CY7C1481V33 CY7C1483V33 CY7C1487V33 -100 Min. 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns Document #: 38-05284 Rev. *A Page 21 of 30 PRELIMINARY Switching Waveforms Write Cycle Timing[19,20] Single Write tCH tCYC Burst Write CY7C1481V33 CY7C1483V33 CY7C1487V33 Pipelined Write Unselected CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS tADH ADSC initiated write ADSC tADVS tADVH ADV tAS ADV Must Be Inactive for ADSP Write WD1 tAH WD2 WD3 ADD GW tWS tWH tWS CE1 masks ADSP tWH WE tCES tCEH CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDS tDH High-Z Data In High-Z 1a 1a 2a = UNDEFINED 2b 2c 2d 3a = DON'T CARE Notes: 19. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table). 20. WDx stands for Write Data to Address X. Document #: 38-05284 Rev. *A Page 22 of 30 PRELIMINARY Switching Waveforms (continued) Read Cycle Timing[19, 21] Single Read tCYC Burst Read tCH CY7C1481V33 CY7C1483V33 CY7C1487V33 Unselected Pipelined Read CLK tADS tADH tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH tADVH RD1 tAH RD2 RD3 Suspend Burst ADV tAS ADD GW tWS tWH tWS WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES tCEH tEOV tCDV tOEHZ 2a tCLZ tCHZ = DON'T CARE Note: 21. RDx stands for Read Data from Address X. OE tDOH 2b 2c 2c 2d 3a Data Out 1a 1a = UNDEFINED Document #: 38-05284 Rev. *A Page 23 of 30 PRELIMINARY Switching Waveforms (continued) Read/Write Timing tCH tCYC tCL CY7C1481V33 CY7C1483V33 CY7C1487V33 CLK tAS tAH B C D ADD A tADS tADH ADSP tADS tADH ADSC tADVS tADVH ADV tCES tCEH CE1 tCES tCEH CE tWES tWEH WE ADSP ignored with CE1 HIGH tEOHZ Q(A) Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D) OE tCLZ Data In/Out tCDV tDOH tCHZ Device originally deselected WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON'T CARE = UNDEFINED Notes: 22. Device originally deselected. 23. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. Document #: 38-05284 Rev. *A Page 24 of 30 PRELIMINARY Switching Waveforms (continued) OE Timing CY7C1481V33 CY7C1483V33 CY7C1487V33 OE tEOHZ tEOV I/Os Three-state tEOLZ Ordering Information Speed (MHz) 150 Ordering Code CY7C1481V33-150AC CY7C1483V33-150AC CY7C1481V33-150BGC CY7C1483V33-150BGC CY7C1481V33-150BZC CY7C1483V33-150BZC CY7C1487V33-150BGC 133 CY7C1481V33-133AC CY7C1483V33-133AC CY7C1481V33-133BGC CY7C1483V33-133BGC CY7C1481V33-133BZC CY7C1483V33-133BZC CY7C1487V33-133BGC 117 CY7C1481V33-117AC CY7C1483V33-117AC CY7C1481V33-117BGC CY7C1483V33-117BGC CY7C1481V33-117BZC CY7C1483V33-117BZC CY7C1487V33-117BGC 100 CY7C1481V33-100AC CY7C1483V33-100AC CY7C1481V33-100BGC CY7C1483V33-100BGC CY7C1481V33-100BZC CY7C1483V33-100BZC CY7C1487V33-100BGC Package Name A101 BG119 BB165C BG209 A101 BG119 BB165C BG209 A101 BG119 BB165C BG209 A101 BG119 BB165C BG209 Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Ball BGA (14 x 22 x 2.4 mm) 165-Ball FBGA (15 x 17 mm) 209-Ball BGA (14 x 22 x 2.2mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Ball BGA (14 x 22 x 2.4 mm) 165-Ball FBGA (15 x 17 mm) 209-Ball BGA (14 x 22 x 2.2mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Ball BGA (14 x 22 x 2.4 mm) 165-Ball FBGA (15 x 17 mm) 209-Ball BGA (14 x 22 x 2.2mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Ball BGA (14 x 22 x 2.4 mm) 165-Ball FBGA (15 x 17 mm) 209-Ball BGA (14 x 22 x 2.2mm) Operating Range Commercial Document #: 38-05284 Rev. *A Page 25 of 30 PRELIMINARY Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 CY7C1481V33 CY7C1483V33 CY7C1487V33 51-85050-A Document #: 38-05284 Rev. *A Page 26 of 30 PRELIMINARY Package Diagrams (continued) 165-Ball FBGA (15 x 17 x 1.20 mm) BB165C CY7C1481V33 CY7C1483V33 CY7C1487V33 51-85165-** Document #: 38-05284 Rev. *A Page 27 of 30 PRELIMINARY Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 CY7C1481V33 CY7C1483V33 CY7C1487V33 51-85115-*B Document #: 38-05284 Rev. *A Page 28 of 30 PRELIMINARY Package Diagrams (continued) 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 CY7C1481V33 CY7C1483V33 CY7C1487V33 51-85143-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05284 Rev. *A Page 29 of 30 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document History Page CY7C1481V33 CY7C1483V33 CY7C1487V33 Document Title: CY7C1481V33/CY7C1483V33/CY7C1487V33 2M x 36/4M x 18/1M x 72 Flow-through SRAM Document Number: 38-05284 REV. ** *A ECN NO. 114671 118283 Issue Date 08/12/02 01/27/03 Orig. of Change PKS HGK New Data Sheet Updated Ordering Information Updated the features for package offering Changed from Advance Information to Preliminary Description of Change Document #: 38-05284 Rev. *A Page 30 of 30 |
Price & Availability of CY7C1487V33-150BGC
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